1. Field of the Invention
The invention relates to a method for fabricating fin-shaped field effect transistor (FinFET), and more particularly to a method of forming silicon cap after forming contact vias and exposing the epitaxial layer.
2. Description of the Prior Art
In recent years, as various kinds of consumer electronic products have continuously improved and been miniaturized, the size of semiconductor components has reduced accordingly, in order to meet requirements of high integration, high performance, and low power consumption.
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
In conventional process for fabricating FinFETs, formation of a silicon cap is typically performed as soon as epitaxial layers are formed. However, this approach often causes bump issues on surface of the polysilicon gate. Moreover, during the fabrication of salicides, problems such as encroachment is caused on the liner between the gate and the spacer as a result of wet clean, which further results in nickel silicide piping. Hence, how to improve the current process to resolve the aforementioned issues has become an important task in this field.